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BRM1553ERL Block Diagram
BRM1553ERL Block Diagram

Part# BRM1553ERL-RND

(ERL IP Core)

MIL-STD-1553 BC/RT/MT Extended Reliability, Intellectual Property Core for FPGA


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MIL-STD-1553B Notice 2 Remote Terminal and Bus Controller, Extended Reliability, IP Core for FPGA Devices, Development License, Including 10 Prototype Units

The BC/RT 1553ERL IP core is designed for MIL-STD-1553 applications requiring extreme reliability. The IP core is available in several configurations such as RT and BC, and several interfaces - Front End or DDC® Enhanced Mini-ACE® Compatible.

Back End Interface
The RT1553ERL can come in different interfaces:
Simple Front-End
DDC® Enhanced Mini-ACE® driver compatible

Gate Count
A small gate count is required from an FPGA device even for complex applications, minimizing cost and the space required on the target board.

Manchester Decoder
The unique Manchester decoder can work with any even clock frequency from 12Mhz and up to reduce clock sources and clock domains onboard (reduces EMI/RFI). Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh environments.

Transceivers
The BC/RT 1553ERL IP core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.

RT Validation
The BC/RT 1553ERL IP core has been successfully implemented in a 3rd party FPGA, and has passed the full MIL-STD-1553B Notice 2 RT Validation test plan in an independent laboratory.

* DDC® and Mini-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is no affiliation between Data Device Corporation and Sital Technology, Ltd or Sealevel Systems Inc. Sealevel is the licensed partner of Sital Technologies, Kfar-Saba, Israel, for distribution in the United States of Sital MIL-STD-1553 products and IP core products.
Compatibility MIL-STD-1553B
Feature Summary:
  • • Extended Reliability State machine, suitable for space applications
  • • MIL-STD-1553 Intellectual Property for FPGAs and ASIC
  • • Suitable for any MIL-STD-1553 RT or BC implementation
  • • Very small FPGA area utilization
  • • Supports any Radiation-Hard FPGA
  • • Supports any even clock frequency
  • • Does not require CPU for management, no software required
  • • Modular architecture allowing flexible implementations
  • • Provided with extended verification environment
  • • Passed full validation testing by 3rd party
  • • Eliminates risks related to parts obsolescence
  • • Based on vendor and technology independent VHDL code
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