MIL-STD-1553 BC/RT/MT Intellectual Property Core for FPGA

Part: BRM1553D-RND   Model: FPGA IP Core

Call for price

Need some help? Contact us


MIL-STD-1553B Notice 2 Bus Controller, Remote Terminal, Bus monitor IP Core for FPGA and ASIC Devices, Development License, Including 10 Prototype Units

The BRM1553D IP core adds MIL-STD-1553 functionality suitable for any MIL-STD-1553 implementation to an FPGA. The core incorporates a back end logic that arranges the messages in a predefined memory and registers structure, which simplifies the interface between the MIL-STD-1553 bus and the local CPU. The BRM1553D core can act as a replacement (2nd source) for DDC® Enhanced Mini-ACE® devices as the data is arranged in the same way.

Back End Interface
Includes DDC® Enhanced Mini-ACE® interface, compatible with existing drivers and applications.

  • No need to rewrite drivers’ code
  • Eliminates replacement risk

Gate Count
A small gate count is required from an FPGA device even for complex applications, minimizing cost and the space required on the target board.

Manchester Decoder
The unique Manchester decoder can work with any clock frequency from 12Mhz and up to reduce clock sources and clock domains onboard (reduces EMI/RFI) and ease the integration with back-end interface. Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh environments.

The BRM1553D IP core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.

* DDC® and Mini-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is no affiliation between Data Device Corporation and Sital Technology, Ltd or Sealevel Systems Inc. Sealevel is the licensed partner of Sital Technologies, Kfar-Saba, Israel, for distribution in the United States of Sital MIL-STD-1553 products and IP core products.


Additional information



Feature Summary:

  • MIL-STD-1553 Intellectual Property for FPGAs and ASIC
  • Suitable for any MIL-STD-1553 BC, RT, MT implementation
  • Compatible to DDC® ACE® and Enhanced Mini-ACE® interface and functionality, works with existing software drivers
  • Eliminates risks related to parts obsolescence
  • Small FPGA area utilization
  • Supports any clock frequency, reduces clock domains
  • Modular architecture allowing flexible implementations
  • Provided with full verification environment
  • Passed full RT validation testing by 3rd party
  • Based on vendor and technology independent VHDL code


There are no reviews yet.

Be the first to review “FPGA IP Core”

Your email address will not be published. Required fields are marked *