MIL-STD-1553B Notice 2 Remote Terminal and Bus Controller, Extended Reliability, IP Core for FPGA Devices, Development License, Including 10 Prototype Units
The BC/RT 1553ERL IP core is designed for MIL-STD-1553 applications requiring extreme reliability. The IP core is available in several configurations such as RT and BC, and several interfaces – Front End or DDC® Enhanced Mini-ACE® Compatible.
A small gate count is required from an FPGA device even for complex applications, minimizing cost and the space required on the target board.
The unique Manchester decoder can work with any even clock frequency from 12Mhz and up to reduce clock sources and clock domains onboard (reduces EMI/RFI). Advanced algorithms for filtering out noise and disturbances enable the core to operate in harsh environments.
The BC/RT 1553ERL IP core connects to any standard transceiver-transformer pair. The core was fully validated with a 3rd party dual transceiver.
The BC/RT 1553ERL IP core has been successfully implemented in a 3rd party FPGA, and has passed the full MIL-STD-1553B Notice 2 RT Validation test plan in an independent laboratory.
* DDC® and Mini-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is no affiliation between Data Device Corporation and Sital Technology, Ltd or Sealevel Systems Inc. Sealevel is the licensed partner of Sital Technologies, Kfar-Saba, Israel, for distribution in the United States of Sital MIL-STD-1553 products and IP core products.